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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 1999 mos integrated circuit m pd4382161, 4382181, 4382321, 4382361 8m-bit cmos synchronous fast sram flow through operation document no. m14019ej5v0ds00 (5th edition) date published june 2000 ns cp(k) printed in japan data sheet the mark h h h h shows major revised points. description the m pd4382161 is a 524,288-word by 16-bit, the m pd4382181 is a 524,288-word by 18-bit, the m pd4382321 is a 262,144-word by 32-bit and the m pd4382361 is a 262,144-word by 36-bit synchronous static ram fabricated with advanced cmos technology using n-channel four-transistor memory cell. the m pd4382161, m pd4382181, m pd4382321 and m pd4382361 integrate unique synchronous peripheral circuitry, 2-bit burst counter and output buffer as well as sram core. all input registers are controlled by a positive edge of the single clock input (clk). the m pd4382161, m pd4382181, m pd4382321 and m pd4382361 are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory. zz has to be set low at the normal operation. when zz is set high, the sram enters power down state (sleep). in the sleep state, the sram internal state is preserved. when zz is set low again, the sram resumes normal operation. the m pd4382161, m pd4382181, m pd4382321 and m pd4382361 are packaged in 100-pin plastic lqfp with a 1.4 mm package thickness for high density and low capacitive loading. features single 3.3 v power supply synchronous operation internally self-timed write control burst read / write : interleaved burst and linear burst sequence fully registered inputs for flow through operation all registers triggered off positive clock edge lvttl compatible : all inputs and outputs fast clock access time : 8.5 ns (100 mhz), 9 ns (90 mhz) ( m pd4382321, m pd4382361) 9 ns (90 mhz), 10 ns (83 mhz) ( m pd4382161, m pd4382181) asynchronous output enable : /g burst sequence selectable : mode sleep mode : zz (zz = open or low : normal operation) separate byte write enable : /bw1 - /bw4 ( m pd4382321, m pd4382361), /bw1 - /bw2 ( m pd4382161, m pd4382181), /bwe global write enable : /gw three chip enables for easy depth expansion common i/o using three state outputs h
2 m pd4382161, 4382181, 4382321, 4382361 data sheet m14019ej5v0ds00 ordering information part number access time ns clock frequency mhz core supply voltage v i/o interface v package notes m pd4382161gf-a90 9.0 90 3.3 0.165 3.3 lvttl 100-pin plastic lqfp (14 x 20) 1 m pd4382161gf-a10 10.0 83 m pd4382181gf-a90 9.0 90 m pd4382181gf-a10 10.0 83 m pd4382321gf-a85 8.5 100 2 m pd4382321gf-a90 9.0 90 m pd4382361gf-a85 8.5 100 m pd4382361gf-a90 9.0 90 notes 1. grade a90 and a10 are available in the m pd4382161gf and m pd4382181gf 2. grade a85 and a90 are available in the m pd4382321gf and m pd4382361gf h h
3 m pd4382161, 4382181, 4382321, 4382361 data sheet m14019ej5v0ds00 pin configurations (marking side) / indicates active low signal. 100-pin plastic lqfp (14 x 20) [ m m m m pd4382161gf, m m m m pd4382181gf] nc nc nc v dd q v ss q nc nc i/o9 i/o10 v ss q v dd q i/o11 i/o12 nc v dd nc v ss i/o13 i/o14 v dd q v ss q i/o15 i/o16 i/op2, nc nc v ss q v dd q nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 a18 nc nc v dd q v ss q nc i/op1, nc i/o8 i/o7 v ss q v dd q i/o6 i/o5 v ss nc v dd zz i/o4 i/o3 v dd q v ss q i/o2 i/o1 nc nc v ss q v dd q nc nc nc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 a6 a7 /ce ce2 nc nc /bw2 /bw1 /ce2 v dd v ss clk /gw /bwe /g /ac /ap /adv a8 a9 mode a5 a4 a3 a2 a1 a0 nc nc v ss v dd nc a17 a10 a11 a12 a13 a14 a15 a16 remark refer to package drawing for 1-pin index mark.
4 m pd4382161, 4382181, 4382321, 4382361 data sheet m14019ej5v0ds00 pin identification ( m m m m pd4382161gf, m m m m pd4382181gf) symbol pin no. description a0 - a18 37, 36, 35, 34, 33, 32, 100, 99, 82, synchronous address input 81, 44, 45, 46, 47, 48, 49, 50, 43, 80 i/o1 - i/o16 58, 59, 62, 63, 68, 69, 72, 73, 8, 9, synchronous data in, 12, 13, 18, 19, 22, 23 synchronous / asynchronous data out i/op1, nc note 74 synchronous data in (parity), i/op2, nc note 24 synchronous / asynchronous data out (parity) /adv 83 synchronous burst address advance input /ap 84 synchronous address status processor input /ac 85 synchronous address status controller input /ce, ce2, /ce2 98, 97, 92 synchronous chip enable input /bw1, /bw2, /bwe 93, 94, 87 synchronous byte write enable input /gw 88 synchronous global write input /g 86 asynchronous output enable input clk 89 clock input mode 31 asynchronous burst sequence select input do not change state during normal operation zz 64 asynchronous power down state input v dd 15, 41, 65, 91 power supply v ss 17, 40, 67, 90 ground v dd q 4, 11, 20, 27, 54, 61, 70, 77 output buffer power supply v ss q 5, 10, 21, 26, 55, 60, 71, 76 output buffer ground nc 1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, no connection 38, 39, 42, 51, 52, 53, 56, 57, 66, 75, 78, 79, 95, 96 note nc (no connection) is used in the m pd4382161gf. i/op1 - i/op2 is used in the m pd4382181gf.
5 m pd4382161, 4382181, 4382321, 4382361 data sheet m14019ej5v0ds00 100-pin plastic lqfp (14 x 20) [ m m m m pd4382321gf, m m m m pd4382361gf] i/op3, nc i/o17 i/o18 v dd q v ss q i/o19 i/o20 i/o21 i/o22 v ss q v dd q i/o23 i/o24 nc v dd nc v ss i/o25 i/o26 v dd q v ss q i/o27 i/o28 i/o29 i/o30 v ss q v dd q i/o31 i/o32 i/op4, nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 i/op2, nc i/o16 i/o15 v dd q v ss q i/o14 i/o13 i/o12 i/o11 v ss q v dd q i/o10 i/o9 v ss nc v dd zz i/o8 i/o7 v dd q v ss q i/o6 i/o5 i/o4 i/o3 v ss q v dd q i/o2 i/o1 i/op1, nc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 a6 a7 /ce ce2 /bw4 /bw3 /bw2 /bw1 /ce2 v dd v ss clk /gw /bwe /g /ac /ap /adv a8 a9 mode a5 a4 a3 a2 a1 a0 nc nc v ss v dd nc a17 a10 a11 a12 a13 a14 a15 a16 remark refer to package drawing for 1-pin index mark.
6 m pd4382161, 4382181, 4382321, 4382361 data sheet m14019ej5v0ds00 pin identification ( m m m m pd4382321gf, m m m m pd4382361gf) symbol pin no. description a0 - a17 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, synchronous address input 45, 46, 47, 48, 49, 50, 43 i/o1 - i/o32 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, synchronous data in, 73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, synchronous / asynchronous data out 18, 19, 22, 23, 24, 25, 28, 29 i/op1, nc note 51 synchronous data in (parity), i/op2, nc note 80 synchronous / asynchronous data out (parity) i/op3, nc note 1 i/op4, nc note 30 /adv 83 synchronous burst address advance input /ap 84 synchronous address status processor input /ac 85 synchronous address status controller input /ce, ce2, /ce2 98, 97, 92 synchronous chip enable input /bw1 - /bw4, /bwe 93, 94, 95, 96, 87 synchronous byte write enable input /gw 88 synchronous global write input /g 86 asynchronous output enable input clk 89 clock input mode 31 asynchronous burst sequence select input do not change state during normal operation zz 64 asynchronous power down state input v dd 15, 41, 65, 91 power supply v ss 17, 40, 67, 90 ground v dd q 4, 11, 20, 27, 54, 61, 70, 77 output buffer power supply v ss q 5, 10, 21, 26, 55, 60, 71, 76 output buffer ground nc 14, 16, 38, 39, 42, 66 no connection note nc (no connection) is used in the m pd4382321gf. i/op1 - i/op4 is used in the m pd4382361gf.
7 m pd4382161, 4382181, 4382321, 4382361 data sheet m14019ej5v0ds00 block diagrams [ m m m m pd4382161, m m m m pd4382181] address register binary counter and logic clr q0 q1 byte 1 write register byte 1 write driver 8/9 byte 2 write register byte 2 write driver 8/9 enable register row and column input register output buffer 19 19 17 19 a0, a1 a1 a0 2 16/18 a0 - a18 mode /adv clk /ac /ap /bw1 /bw2 /bwe /gw /ce ce2 /ce2 /g i/o1 - i/o16 i/op1 - i/op2 zz power down control 16/18 16/18 memory cell array 1,024 rows 512 16 columns (8,388,608 bits) 512 18 columns (9,437,184 bits) decoders burst sequence [ m m m m pd4382161, m m m m pd4382181] interleaved burst sequence table (mode = open or v dd ) external address a18 - a2, a1, a0 1st burst address a18 - a2, a1, /a0 2nd burst address a18 - a2, /a1, a0 3rd burst address a18 - a2, /a1, /a0 linear burst sequence table (mode = v ss ) external address a18 - a2, 0, 0 a18 - a2, 0, 1 a18 - a2, 1, 0 a18 - a2, 1, 1 1st burst address a18 - a2, 0, 1 a18 - a2, 1, 0 a18 - a2, 1, 1 a18 - a2, 0, 0 2nd burst address a18 - a2, 1, 0 a18 - a2, 1, 1 a18 - a2, 0, 0 a18 - a2, 0, 1 3rd burst address a18 - a2, 1, 1 a18 - a2, 0, 0 a18 - a2, 0, 1 a18 - a2, 1, 0
8 m pd4382161, 4382181, 4382321, 4382361 data sheet m14019ej5v0ds00 [ m m m m pd4382321, m m m m pd4382361] address register binary counter and logic clr q0 q1 byte 1 write register byte 1 write driver 8/9 byte 2 write register byte 2 write driver 8/9 byte 3 write register byte 3 write driver 8/9 byte 4 write register byte 4 write driver 8/9 enable register row and column input register output buffer 32/36 18 18 16 18 a0, a1 a1 a0 32/36 4 32/36 a0 - a17 mode /adv clk /ac /ap /bw1 /bw2 /bw3 /bw4 /bwe /gw /ce ce2 /ce2 /g i/o1 - i/o32 i/op1 - i/op4 zz power down control memory cell array 1,024 rows 256 32 columns (8,388,608 bits) 256 36 columns (9,437,184 bits) decoders burst sequence [ m m m m pd4382321, m m m m pd4382361] interleaved burst sequence table (mode = open or v dd ) external address a17 - a2, a1, a0 1st burst address a17 - a2, a1, /a0 2nd burst address a17 - a2, /a1, a0 3rd burst address a17 - a2, /a1, /a0 linear burst sequence table (mode = v ss ) external address a17 - a2, 0, 0 a17 - a2, 0, 1 a17 - a2, 1, 0 a17 - a2, 1, 1 1st burst address a17 - a2, 0, 1 a17 - a2, 1, 0 a17 - a2, 1, 1 a17 - a2, 0, 0 2nd burst address a17 - a2, 1, 0 a17 - a2, 1, 1 a17 - a2, 0, 0 a17 - a2, 0, 1 3rd burst address a17 - a2, 1, 1 a17 - a2, 0, 0 a17 - a2, 0, 1 a17 - a2, 1, 0
9 m pd4382161, 4382181, 4382321, 4382361 data sheet m14019ej5v0ds00 asynchronous truth table operation /g i/o read cycle l dout read cycle h hi-z write cycle hi-z, din deselected hi-z remark : dont care synchronous truth table operation /ce ce2 /ce2 /ap /ac /adv /write clk address deselected note h l l ? h none deselected note ll l l ? h none deselected note l hl l ? h none deselected note ll hl l ? h none deselected note l hhl l ? h none read cycle / begin burst l h l l l ? h external read cycle / begin burst l h l h l hl ? h external read cycle / continue burst hh l l ? hnext read cycle / continue burst h hl l ? hnext read cycle / suspend burst hh h l ? h current read cycle / suspend burst h hh l ? h current write cycle / begin burst l h l h l ll ? h external write cycle / continue burst hh l l ? hnext write cycle / continue burst h hl l ? hnext write cycle / suspend burst hh h l ? h current write cycle / suspend burst h hh l ? h current note deselect status is held until new begin burst entry. remarks 1. : dont care 2. /write = l means any one or more byte write enables (/bw1, /bw2, /bw3 or /bw4) and /bwe are low or /gw is low. /write = h means the following two cases. (1) /bwe and /gw are high. (2) /bw1, /bw2, /bw3, /bw4 and /gw are high, and /bwe is low.
10 m pd4382161, 4382181, 4382321, 4382361 data sheet m14019ej5v0ds00 partial truth table for write enables [ m m m m pd4382161, m m m m pd4382181] operation /gw /bwe /bw1 /bw2 read cycle h h read cycle h l h h write cycle / byte 1 only h l l h write cycle / all bytes h l l l write cycle / all bytes l remark : dont care [ m m m m pd4382321, m m m m pd4382361] operation /gw /bwe /bw1 /bw2 /bw3 /bw4 read cycle h h read cycle h l h h h h write cycle / byte 1 only h l l h h h write cycle / all bytes h l l l l l write cycle / all bytes l remark : dont care zz (sleep) truth table zz chip status 0.2 v active open active 3 v dd - 0.2 v sleep
11 m pd4382161, 4382181, 4382321, 4382361 data sheet m14019ej5v0ds00 electrical specifications absolute maximum ratings parameter symbol conditions min. typ. max. unit note supply voltage v dd C0.5 +4.0 v output supply voltage v dd q C0.5 v dd v input voltage v in C0.5 v dd + 0.5 v 1, 2 input / output voltage v i/o C0.5 v dd q + 0.5 v 1, 2 operating ambient temperature t a 070c storage temperature t stg C55 +125 c notes 1. C2.0 v (min.)(pulse width : 2 ns) 2. v dd q + 2.3 v (max.)(pulse width : 2 ns) caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc operating conditions (t a = 0 to 70 c) parameter symbol conditions min. typ. max. unit supply voltage v dd 3.135 3.3 3.465 v output supply voltage v dd q 3.135 3.3 3.465 v high level input voltage v ih 2.0 v dd q + 0.3 v low level input voltage v il C0.3 note +0.8 v note C0.8 v (min.)(pulse width : 2 ns) capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c in v in = 0 v 4 pf input / output capacitance c i/o v i/o = 0 v 7 pf clock input capacitance c clk v clk = 0 v 4 pf remark these parameters are periodically sampled and not 100 % tested.
12 m pd4382161, 4382181, 4382321, 4382361 data sheet m14019ej5v0ds00 dc characteristics (t a = 0 to 70 c, v dd = 3.3 v 0.165 v) parameter symbol test condition min. typ. max. unit note input leakage current i li v in (except zz, mode) = 0 v to v dd C2 +2 m a i/o leakage current i lo v i/o = 0 v to v dd q, outputs are disabled. C2 +2 m a operating supply current i dd device selected, m pd4382161-a90 250 ma cycle = max. m pd4382181-a90 v in v il or v in 3 v ih , m pd4382161-a10 240 i i/o = 0 ma m pd4382181-a10 m pd4382321-a85 350 m pd4382361-a85 m pd4382321-a90 330 m pd4382361-a90 i dd1 suspend cycle, cycle = max. 120 /ac, /ap, /adv, /gw, /bwes 3 v ih v in v il or v in 3 v ih , i i/o = 0 ma standby supply current i sb device deselected, cycle = 0 mhz 30 ma v in v il or v in 3 v ih , all inputs are static. i sb1 device deselected, cycle = 0 mhz 10 v in 0.2 v or v in 3 v dd C 0.2 v v i/o 0.2 v, all inputs are static. i sb2 device deselected, cycle = max. 150 v in v il or v in 3 v ih power down supply current i sbzz zz 3 v dd C 0.2 v, v i/o v dd q + 0.2 v 10 ma high level output voltage v oh i oh = C4.0 ma 2.4 v low level output voltage v ol i ol = +8.0 ma 0.4 v h h
13 m pd4382161, 4382181, 4382321, 4382361 data sheet m14019ej5v0ds00 ac characteristics (t a = 0 to 70 c, v dd = 3.3 v 0.165 v) ac test conditions input waveform (rise / fall time 3.0 ns) test points v ss 3.0 v 1.5 v 1.5 v output waveform test points 1.5 v 1.5 v output load condition c l : 30 pf 5 pf (tkhqx1, tkhqx2, tglqx, tghqz, tkhqz) external load at test v t = +1.5 v i/o (output) 50 w z o = 50 w c l remark c l includes capacitances of the probe and jig, and stray capacitances.
14 m pd4382161, 4382181, 4382321, 4382361 data sheet m14019ej5v0ds00 read and write cycle parameter symbol -a85 -a90 -a10 unit note (100 mhz) (90 mhz) (83 mhz) standard alias min. max. min. max. min. max. cycle time tkhkh tcyc 10 C 11 C 12 C ns clock access time tkhqv tcd C 8.5 C 9 C 10 ns output enable access time tglqv toe C 3.5 C 3.5 C 4.8 ns clock high to output active tkhqx1 tdc1 2 C 2 C 2 C ns clock high to output change tkhqx2 tdc2 3 C 3 C 3 C ns output enable to output active tglqx tolz 0 C 0 C 0 C ns output disable to output high-z tghqz tohz 0 3.5 0 3.5 0 3.5 ns clock high to output high-z tkhqz tcz 2 4 2 4 2 4 ns clock high pulse width tkhkl tch 2.5 C 2.5 C 2.5 C ns clock low pulse width tklkh tcl 2.5 C 2.5 C 2.5 C ns setup times address tavkh tas 2 C 2 C 2.5 C ns address status tadsvkh tss data in tdvkh tds write enable twvkh tws address advance tadvvkh C chip enable tevkh C hold times address tkhax tah 0.5 C 0.5 C 0.5 C ns address status tkhadsx tsh data in tkhdx tdh write enable tkhwx twh address advance tkhadvx C chip enable tkhex C power down entry setup tzzes tzzes 5 C 5 C 5 C ns 1 power down entry hold tzzeh tzzeh 1 C 1 C 1 C ns 1 power down recovery setup tzzrs tzzrs 6 C 6 C 6 C ns 1 power down recovery hold tzzrh tzzrh 0 C 0 C 0 C ns 1 note 1. although zz signal input is asynchronous, the signal must meet specified setup and hold times in order to be recognized. h
15 m pd4382161, 4382181, 4382321, 4382361 data sheet m14019ej5v0ds00 tkhkh tklkh tkhax twvkh tkhwx tkhex tglqv tglqx tkhqx2 tkhqz q1(a1) q1(a2) q2(a2) q3(a2) q4(a2) q1(a3) hi-z a1 a2 a3 clk /ap /ac address /adv /ces note /g data in /bwe /bws tghqz tkhqv tkhkl tkhadsx tadsvkh tavkh tevkh tadsvkh tkhadsx tadvvkh tkhadvx twvkh tkhwx /gw data out read cycle remark qn(a2) refers to output from address a2. q1-q4 refer to outputs according to burst sequence. /ces refers to /ce, ce2 and /ce2. when /ces is low, /ce and /ce2 are low and ce2 is high. when /ces is high, /ce and /ce2 are high and ce2 is low. note q1(a2)
16 m pd4382161, 4382181, 4382321, 4382361 data sheet m14019ej5v0ds00 tkhkh tavkh tkhax tevkh tkhex d1(a1) d1(a2) d2(a2) d2(a2) d3(a2) d4(a2) d1(a3) d2(a3) d3(a3) hi-z tkhkl tklkh a1 a2 a3 tdvkh tkhdx tkhadsx twvkh tkhwx clk /ap /ac address /adv /ces note2 /g data in /bwe note1 /bws /gw note1 data out twvkh tkhadvx tkhwx tadsvkh tkhadsx tadsvkh write cycle notes 2. all bytes write can be initiated by /gw low or /gw high and /bwe, /bw1-/bw4 low. 1. /ces refers to /ce, ce2 and /ce2. when /ces is low, /ce and /ce2 are low and ce2 is high. when /ces is high, /ce and /ce2 are high and ce2 is low. tghqz tadvvkh d2(a1)
17 m pd4382161, 4382181, 4382321, 4382361 data sheet m14019ej5v0ds00 tkhkh tklkh tkhkl tavkh tevkh tkhex tkhqv tglqx q1(a1) q1(a3) q2(a3) q3(a3) a1 tghqz tkhqx1 tdvkh tkhdx hi-z d1(a2) tadsvkh tkhadsx tkhax tadsvkh tkhadsx clk /ap /ac address /adv /ces note2 /g data in /bwe note1 /bws /gw note1 data out twvkh tkhwx twvkh tkhwx q4(a3) tadvvkh tkhadvx notes 2. all bytes write can be initiated by /gw low or /gw high and /bwe, /bw1-/bw4 low. 1. /ces refers to /ce, ce2 and /ce2. when /ces is low, /ce and /ce2 are low and ce2 is high. when /ces is high, /ce and /ce2 are high and ce2 is low. read / write cycle a2 a3
18 m pd4382161, 4382181, 4382321, 4382361 data sheet m14019ej5v0ds00 tkhkh zz tklkh a1 a2 tzzeh tzzes tzzrh tzzrs power down (i sbzz ) state q2(a2) tkhkl clk /ap /ac address /adv /ces /g /bwe /bws /gw data out power down (zz) cycle q1(a2) q1(a1) hi-z
19 m pd4382161, 4382181, 4382321, 4382361 data sheet m14019ej5v0ds00 tkhkh data out tkhkl tklkh a1 a2 power down state (i sb1 ) note q1(a1) q1(a2) data in clk /ap /ac address /adv /ces /g /bwe /bws /gw stop clock cycle hi-z note v in 0.2 v or v in 3 v dd - 0.2 v, v i/o 0.2 v
20 m pd4382161, 4382181, 4382321, 4382361 data sheet m14019ej5v0ds00 package drawing 100-pin plastic lqfp (14x20) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 22.0 0.2 20.0 0.2 0.65 (t.p.) 0.575 j 16.0 0.2 k c 14.0 0.2 i 0.13 1.0 0.2 l 0.5 0.2 f 0.825 n p q 0.10 1.4 0.125 0.075 s100gf-65-8et-1 s 1.7 max. h 0.32 + 0.08 - 0.07 m 0.17 + 0.06 - 0.05 r3 + 7 - 3 m 80 81 51 50 30 31 100 1 s s n j detail of lead end c d a b r k m l p i s q g f h
21 m pd4382161, 4382181, 4382321, 4382361 data sheet m14019ej5v0ds00 recommended soldering condition please consult with our sales offices for soldering conditions of the m pd4382161, 4382181, 4382321 and 4382361. types of surface mount devices m pd4382161 gf : 100-pin plastic lqfp (14 x 20) m pd4382181 gf : 100-pin plastic lqfp (14 x 20) m pd4382321 gf : 100-pin plastic lqfp (14 x 20) m pd4382361 gf : 100-pin plastic lqfp (14 x 20)
22 m pd4382161, 4382181, 4382321, 4382361 data sheet m14019ej5v0ds00 [memo]
23 m pd4382161, 4382181, 4382321, 4382361 data sheet m14019ej5v0ds00 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m pd4382161, 4382181, 4382321, 4382361 m8e 00. 4 the information in this document is current as of june, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above).

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